The present invention relates to metal oxide semiconductor (MOS) devices, and particularly to an offset spacer for MOS device improvement in deep sub-micron processes.
The trend in developing very large scale integration (VLSI) circuits is towards devices having smaller line width on a larger silicon chip, thus more functions can be integrated into an integrated circuit within a given size. Current efforts continue to design semiconductor devices, such as metal-oxide-semiconductor field effect transistors (MOSFETs), which occupy less physical space, consume less power and operate at higher switching speed at lower voltage. Miniaturization of MOS device brings the source and drain terminals closer to each other. When the channel length is reduced, the degree of overlapping of the depletion region in the source/drain terminal with the channel is increased. Hot-electron effect usually accompanies in the reduced channel length and affects operation speed of the MOS device. To resolve the problems, advanced CMOS processes add a lightly doped drain (LDD) region between the channel region and each source/drain region to minimize hot-electron effect, especially if the devices are NMOS devices. Nevertheless, the high concentration LDD terminals often result in large overlapping with a gate conductive layer after annealing and thermal treatments. When appropriate bias voltages are applied to the MOSFET structure, an overlap capacitance developed in an area between the gate conductive layer and the LDD region can lead to abnormal bias and a reduction of AC performance of the device.
An offset spacer developed on sidewalls of the gate conductive layer is used to lower the overlap capacitance between the gate conductive layer and the LDD region, thereby increasing operation speed, reducing gate leakage and improving drain-induced barrier lowering (DIBL) effect in the MOSFET structure. The thickness of the offset spacer is modified to adjust the channel length and improve the punch-through margins. In U.S. Pat. No. 5,981,325 a channel length adjustment procedure using offset spacers is taught. In U.S. Pat. No. 6,187,645 a method of preventing gate-to-drain capacitance in a MOS device with offset spacers is described.
FIGS. 1A through 1C are cross-sectional diagrams illustrating a conventional method of forming a MOS transistor with offset spacers on sidewalls of a gate conductive layer. In FIG. 1A, a semiconductor silicon substrate 10 is provided with a gate oxide layer 12 and a gate conductive layer 14 patterned thereon successively. A chemical vapor deposition (CVD) process is performed to form a silicon oxide layer 16 of 20˜40 Angstroms thick, and then a silicon nitride layer 18 of 100˜150 Angstroms thick is conformally deposited on the silicon oxide layer 16.
In FIG. 1B, a dry etch process is used to remove certain portions of the silicon nitride layer 18 and the silicon oxide layer 16, thus remaining portions 18″ and 16″ of the silicon nitride layer 18 and the silicon oxide layer 16 along the sidewalls of the gate conductive layer 14. The silicon nitride layer 18″ along the sidewalls of the gate conductive layer 14 is an offset spacer for a subsequent LDD ion implantation process. The silicon oxide layer 16″ is a buffer layer for a stress-release issue of the silicon nitride offset spacer 18″. An ion implantation process 22 is then performed with the silicon nitride offset spacer 18″ as the mask to implant ions into the substrate 10, resulting in LDD regions 24 laterally adjacent to the exterior sidewalls of the silicon nitride offset spacer 18″. In FIG. 1C, a main spacer structure 30 including a silicon oxide layer 26 and a silicon nitride layer 28 is formed on the exterior sidewalls of the silicon nitride offset spacer 18″ by dielectric deposition and dry etch processes. Finally, an ion implantation process 32 is performed with the main spacer structure 30 as the mask to implant ions into the substrate 10, resulting in source/drain regions 34 laterally adjacent to the exterior sidewalls of the main spacer structure 30.
The aforementioned offset spacer formation, typically including deposition and dry etch processes, is a complex procedure with poor stability and high cost. As device size decreases below about 0.13 microns, the deposition and etching processes have extremely narrow process windows whereby dimensional variation undesirably alters critical dimension (CD) and electrical performance of the MOSFET device. Following the dry etch process for the offset spacer formation, an oxide stripping process with wet chemical immersion (e.g., in Caro's acid) causes the silicon substrate to suffer from surface damage and silicon loss, which becomes more serious when a post-LDD implant wet clean is subsequently carried out. In addition, considering a high-temperature annealing followed by the ion implantation process 22 for activating the implanted dopants of the LDD regions 24, problems of dosage control and dosage contamination still need to overcome.
Accordingly, what is needed in the art is a device and a method of manufacture thereof that accesses the above-discussed issues.